The invention relates to the general field of integrated circuit packaging with particular reference to low cost methods for packaging individual chips.
Manufacturing techniques in use in the semiconductor industry have continued to improve in efficiency with resulting drops in cost. This is particularly true for chip manufacturing where the cost per gate continues to drop year by year. Some of this advantage is, however, offset by the somewhat slower pace at which the cost of chip packaging has been dropping. Until recently, chip manufacture and chip packaging have been treated as essentially separate technologies and advances in the former have not necessarily added value to the latter.
Recently, wafer scale packaging has been gaining in popularity. By this we mean that the entire wafer is packaged prior to its being separated into individual chips. A good example of this has been a recent publication by M. Hou xe2x80x9cWafer level packaging for CSPsxe2x80x9d in Semiconductor International, July 1998 pp. 305-308. CSPs (chip scale packages) first made their appearance around 1996. Since then there have been a number of improvements exemplified by the structure described by Hou. In the process that she discusses, assembly of individual chip packages becomes an extension of the wafer fabrication line rather than a separate operation dedicated to chip packaging.
Briefly, the process that is described by Hou involves compression molding of an encapsulant onto the top surface of the full wafer. A special molding press, custom built to fit each type of wafer that is to be used, is needed and reliance is made on the ability of the solder bumps, already present on the top surface of the completed wafer, to push through the plastic and reappear at the top surface of the package. Hou notes that this approach is suited primarily to low density packages.
It has been an object of the present invention to provide a package and a process for packaging semiconductor chips.
An additional object of the invention has been that said process result in the simultaneous packaging of all chips on a single wafer at the same time.
A still further object of the invention has been that said process not require any special jigs or fixtures for its implementation.
Yet another of object of the invention has been that said process be suitable for packages having a high density of interconnections.
One more object of the invention has been that said process provide packages that are significantly cheaper than those obtained through individual chip packaging processes.
These objects have been achieved by depositing a layer of a polymeric material, such as polyimide, silicone elastomer, or benzocyclobutene on the surface of the chip. Via holes through this layer connect to the top surfaces of the studs that pass through the passivating layer of the chip. In one embodiment, the polymeric layer covers a redistribution network on a previously planarized surface of the chip. Individual chip-level networks are connected together in the kerf so that conductive posts may be formed inside the via holes through electroplating. After the formation of solder bumps, the wafer is diced into individual chips thereby isolating the individual redistribution networks. In a second embodiment, no redistribution network is present. In a third embodiment, there is also no redistribution network but electroplating is made possible by using a contacting layer. The polymeric layer then also serves as the final planarizing layer. Conductive posts are then formed in the via holes by means of electroless plating.